What the IDE does for your SystemVerilog and UVM code

SystemVerilog Studio turns IntelliJ IDEA (Community included) and other JetBrains IDEs into a SystemVerilog and UVM IDE. Each feature below links the guide page that describes it, with steps to try on the guide's sample project.

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rtl/top.sv

8counter #(.MAX(20)) u_counter(.clk, .rst_n, .count(count), .done(done));

rtl/counter.sv

1module counter #(parameter int MAX = 10) (

2input logic clk,

3input logic rst_n,

4output logic [7:0] count,

5output logic done

Go to Declaration

Click a name and press ⌘B (Ctrl+B): the editor opens its declaration, in whichever file it is. Names are resolved the way a SystemVerilog tool resolves them: inner scopes first, then enclosing scopes, base classes, imported packages and the whole project. Two things with the same name in different scopes are never confused, such as a signal data in two modules.

Go to Declaration In the IDE: video

Find: my_item

uvm/my_pkg.sv

12endclass : my_item

14class my_seq extends uvm_sequence #(my_item);

19my_item it;

20it = my_item::type_id::create("it");

27class my_driver extends uvm_driver #(my_item);

10super.new(name);

11endfunction

12endclass : my_item

Find Usages

Put the caret on a declaration, or on a place it is used, and press ⌥F7 (Alt+F7): the Find tool window lists its usages, grouped by file. Usages include end labels, named port and parameter connections, pkg:: references and type arguments such as #(my_item). Text in comments and string literals is not a usage.

Find Usages In the IDE: screenshot

uvm/my_pkg.sv

28`uvm_component_utils(my_driver)

29virtual my_if vif;

…

48class my_agent extends uvm_agent;

49my_driver drv;

…

58class my_env extends uvm_env;

59my_agent agt;

…

64agt.drv.vif = null;

UVM that resolves

UVM testbenches reach their classes through handles, factory calls and config_db string keys. Go to Declaration, Find Usages and Rename follow these patterns, from vif.req to the signal. Strings such as the config_db key "vif" are left alone.

UVM testbenches In the IDE: Find Usages of my_if

rtl/top.sv

8counter #(.MAX(20)) u_counter(.clk, .rst_n, .count(count), .done(done));

`COUNTER(u_counter2, clk, rst_n)

`define COUNTER(__name, __clk, __rst_n) \

Expands to

counter u_counter2 (.clk(clk), .rst_n(rst_n), .count(), .done())

rtl/defines.svh

10genvar i;

See what a macro expands to

SystemVerilog Studio treats a macro like any other declaration: you can jump from a call to its definition, list its calls and rename it in all files. Code | Expand Macro shows the code a call expands to, with your arguments in place. UVM macros expand too, once the UVM sources are in your project.

Macros In the IDE: screenshot

Editing and the slang compiler

rtl/counter.sv

11always_ff @(posedge clk or negedge rst_n) begin : seq

12if (!rst_n) begin

13count <= 0;

14state <= IDEL;

'IDEL' is not declared; did you mean 'IDLE'?

Change to 'IDLE'

15end

16else if (state == COUNT) begin

17count <= count + 1;

Undeclared names, with the fix

SystemVerilog Studio underlines an undeclared name such as IDEL as you type. When a declared name is spelt almost the same, it suggests that name and replaces it for you (⌥⏎ / Alt+Enter). A typo that Verilog would quietly turn into a new 1-bit wire, an implicit net, is reported as a warning, because the file would still compile.

Undeclared names In the IDE: screenshot

rtl/counter.sv

1module counter #(parameter int MAX = 10) (

slang: design element does not have a time scale defined but others in the design do [MissingTimeScale]

2input logic clk,

3input logic rst_n,

4output logic [7:0] count,

5output logic done

6);

Compiler checks with slang

Some mistakes only show up when the whole design is compiled together. Once slang is installed (one click in Settings), SystemVerilog Studio compiles your design with it each time you save a file. Its messages start with slang: and appear in the editor next to the IDE's own checks.

Compiler checks

Design Hierarchy

top top

clk input logic

rst_n input logic

u_counter counter

MAX int = 20

g_lane

[0]

[1]

i integer = 1

The elaborated design hierarchy

The Design Hierarchy tool window shows the design elaborated: built from the top module down as a compiler builds it, with each parameter's actual value and generate loops unrolled. It comes from slang-server, the language server of the slang compiler, which starts in the background when you open the window. Without slang-server, the window shows the static hierarchy instead, with parameters as written.

Design hierarchy Install slang

Code | Expand AUTOs

fifo u_fifo (/*AUTOINST*/

// Outputs

.rd_data (rd_data[WIDTH-1:0]),

.full (full),

.empty (empty),

// Inputs

.clk (clk),

…

.rd_en (rd_en));

verilog-mode AUTOs

Write /*AUTOINST*/ where an instance's port connections go. Code | Expand AUTOs connects each port to a signal of the same name, with vector ranges shown. This is Emacs verilog-mode's AUTO feature, so files written for it open and edit like any other.

Expand AUTOs

Refactoring

classes/shapes.sv

1class shape;

2virtual function real get_area();

…

9virtual function real get_area();

10return side * side;

…

19function real get_area();

20return 3.14 * radius * radius;

…

32$display(s.get_area());

Rename

Renaming with find-and-replace changes things that merely look alike. Rename changes only the names that refer to this declaration, in all files: the declaration and the usages Find Usages would list. Words in comments and strings stay as they are unless you tick Search in comments and strings.

Rename Find Usages In the IDE: video

rtl/counter.sv

7import counter_pkg::*;

9state_t state;

count

Conflicts Detected

'count' is already declared in this scope

Usage of 'state' in 'state <= IDLE' would refer to another declaration of 'count'

CancelRefactor Anyway

Rename conflicts

Before it changes a file, Rename tries the new name with the same lookup rules the IDE uses to resolve names. If the new name would silently break or re-bind code, the Conflicts Detected dialog lists the problems and you can cancel. For example, renaming state to count in the sample project would make state <= IDLE assign to the output port count instead.

Rename conflicts In the IDE: screenshot

Running

Run

…/verilator --lint-only -f …/sim.f

…

%Warning-WIDTHEXPAND: rtl/counter.sv:18:17: Operator EQ expects 32 bits …

%Error: Exiting due to 3 warning(s)

Process finished with exit code 1

rtl/counter.sv

18if (count == MAX - 1) state <= DONE;

Run Verilator and Icarus

SystemVerilog Studio runs Verilator and Icarus Verilog as run configurations, started with the Run button. The output appears in the Run tool window, and each file:line in it is a link to the source. You install the simulators; the IDE runs them.

Run configurations Verilator Icarus Verilog In the IDE: screenshot

Run/Debug Configurations

Namesim_tb

ActionBuild and run

Top modulesim_tb

Verilator options

--trace -Wno-fatal tb/sim_tb.sv

Run

PASS: the counter is done at 225000

- tb/sim_tb.sv:18: Verilog $finish

Process finished with exit code 0

Build and run a testbench with Verilator

A Verilator run configuration does one of three things with your design: Lint it, Build the simulation, or Build and run it. You set the action, the top module and Verilator's options in one dialog, and start it with the Run button. Verilator compiles the design into a C++ program, so it needs a C++ compiler and make next to it on your machine.

Verilator In the IDE: screenshot

sim_tb.vcd

clkcountdone

0d0e0f1011121314

225 ns

See the waves in Surfer

A Waveform Viewer run configuration opens a .vcd or .fst file in Surfer or GTKWave. You go from a run to its waves with one click instead of typing the viewer's command. The viewer is a separate application on your PATH.

Waveform viewer In the IDE: screenshot

Your coding agent asks the IDE too

Your coding agent (Claude Code, Codex, Cursor, Junie) gets the same project knowledge through its MCP tools: references, module interfaces, the elaborated hierarchy, a check of code before it is written, and a dry-run rename.

See what an agent can ask Coding agents (MCP)

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What the IDE does for your SystemVerilog and UVM code

Navigation and UVM

Go to Declaration

Find Usages

UVM that resolves

See what a macro expands to

Editing and the slang compiler

Undeclared names, with the fix

Compiler checks with slang

The elaborated design hierarchy

verilog-mode AUTOs

Refactoring

Rename

Rename conflicts

Running

Run Verilator and Icarus

Build and run a testbench with Verilator

See the waves in Surfer

Your coding agent asks the IDE too

Start with a free 2-month code