Your coding agent asks the IDE.

SystemVerilog Studio gives coding agents (Claude Code, Codex, Cursor, Junie) SystemVerilog tools on the IDE's own MCP server. Instead of guessing from the text with grep, the agent asks the IDE: where is this declared, what ports does this module have, who instantiates it, what does this macro expand to, is this file correct. It can also rename a declaration or expand verilog-mode AUTOs, with a preview first.

Get a free 2-month code Read the setup guide

Design Hierarchy

top top
u_counter counter
MAX int = 20

clkcountdone

slang 12.0.0

sv_hierarchy
sv_find_references
sv_check
sv_run

What an agent can ask

Ask in plain words; the agent picks the tool.

sv_project_info: What the IDE compiles with: the compile file (.f) in use, its defines, include directories and sources, and the problems, such as packages imported or files included that the project does not have.
sv_find_symbol: Declarations by name or by a pattern with * (uvm_*_agent), each with its kind and the file, line and column of its name.
sv_module_interface: What an instance or a call connects to: a module's, interface's or program's parameters and ports in order, with direction, type and width in bits.
sv_find_references: The uses of a declaration across the project, as Find Usages finds them: instances, connections, calls, end labels, imports.
sv_expand_macro: What a macro call expands to, as Code | Expand Macro shows it, with the definitions in effect there.
sv_instances: The static hierarchy around a module, interface or program: the instances of it in the project, and the instances it holds.
sv_drivers: What drives a signal and, with loads, what reads it, each place with its kind (assign, always_ff, …).
sv_expand_autos: verilog-mode AUTOs expanded in the files named; by default a dry run that returns the diff and writes nothing.
sv_rename: A declaration renamed with its uses, as Rename makes it; by default a dry run with the diff, the conflicts and notes.
sv_apply_fix: One of the quick fixes sv_check lists, as the IDE's Alt+Enter applies it; by default a dry run with the diff.
sv_create_compile_file: A compile file (.f) made from a top module, for a project that has none or to compare with yours: the files the top needs.
sv_run: A Verilator or Icarus Verilog run configuration run, with its output parsed: problems, errors, warnings, the UVM report counts and whether it passed. Off by default: it runs only in a trusted project, after you turn on “Agents may run SystemVerilog tools” in Settings. Turning it on lets agents run code, such as what the design and compile files make the tools run.
sv_outline: A file as a compact outline, in place of reading it: its units with their parameters, ports, signals, instances and blocks.
sv_members: The members of a class with its base classes, the fields of a struct or union, or the literals of an enum.
sv_check: The problems in the files named, each with its rule, severity, place and quick fixes; with content, the text the agent intends to write, checked before it is written.
sv_hierarchy: The elaborated design, as the Design Hierarchy shows it: parameters propagated and generate loops unrolled (needs slang-server).
sv_elaborated_drivers: What drives (or reads) a signal in the elaborated design, by its hierarchical path, through ports and per instance (needs slang-server).

All tools, in full

A real answer

You ask: “Check top.sv.” After the agent removed .rst_n from the instance u_counter, sv_check reports the input left unconnected, with the quick fix the IDE offers. This is the answer on the guide's sample project.

sv_check rtl/top.sv

{
  "files": [
    {
      "file": "rtl/top.sv",
      "problems": [
        {
          "line": 8,
          "column": 23,
          "end_line": 8,
          "end_column": 32,
          "severity": "WARNING",
          "rule": "SystemVerilogUnconnectedInputs",
          "message": "Input not connected: 'rst_n'",
          "fixes": [
            "Connect missing ports"
          ],
          "engine": "svstudio"
        }
      ],
      "verdict": "pass",
      "slang": "unavailable"
    }
  ],
  "more": false,
  "timed_out": false,
  "slang": {
    "state": "unavailable",
    "reason": "slang is not installed: set its path in Settings | Languages & Frameworks | SystemVerilog | slang, or download it there"
  }
}

Connect your agent

The tools run on the MCP server that comes with the IDE, in version 2025.2.2 and newer.

In the IDE, open Settings | Tools | MCP Server and check Enable MCP Server. The line shows the server's address.
Connect the agent: click Auto-Configure next to it (Claude Code, Claude App, VS Code), or copy the SSE or Stdio configuration into the agent's settings. For Claude Code, run the command below in your project's folder, with the address the settings show.
Start the agent in the project the IDE has open. In Claude Code, /mcp lists jetbrains as connected, with the sv_ tools among its tools.

Claude Code

claude mcp add --transport sse jetbrains http://127.0.0.1:64342/sse

Connect your agent, step by step

Tell your agent when to use the tools

Agents pick tools better with a few rules about when each one helps: look up an interface before writing an instance, check an edit before writing it, rename instead of search-and-replace. SystemVerilog Studio ships these rules for your agent.

Claude Code: download SKILL.md and save it as .claude/skills/systemverilog-studio/SKILL.md in your project (or in ~/.claude/skills/ for all projects). Create the folders; if the link opens as text, save the page.
Codex, Cursor, Junie and others: paste the contents of AGENTS-systemverilog.md at the end of your project's AGENTS.md, or of the file your agent reads instead.

Both hold the same rules. They are optional.

Where to save them

Try it on your project

Enter your email address and SystemVerilog Studio sends a 2-month code by email. No account or payment details needed.

Get a free 2-month code Try the tools on the sample project