The SystemVerilog IDE your coding agent can use too.

Turns IntelliJ IDEA and other JetBrains IDEs into a SystemVerilog and UVM IDE that your coding agent can use through its MCP tools.

Get a free 2-month code See what an agent can ask

You ask

“Where is the counter declared?”

The agent calls sv_find_symbol counter* and gets:

{
  "symbols": [
    {
      "name": "counter",
      "kind": "module",
      "file": "rtl/counter.sv",
      "line": 1,
      "column": 8
    },

1 more symbol

You ask

“What ports does counter have?”

The agent calls sv_module_interface counter and gets:

"ports": [
  {
    "name": "clk",
    "direction": "input",
    "type": "logic",
    "width": 1
  },

3 more ports

You ask

“Who uses counter?”

The agent calls sv_find_references rtl/counter.sv 1:8 and gets:

"usages": [
  {
    "file": "rtl/counter.sv",
    "line": 24,
    "column": 13,
    "text": "endmodule : counter",
    "container": "counter"
  },

2 more usages

You ask

“Check top.sv.”

The agent calls sv_check rtl/top.sv and gets:

"problems": [
  {
    "line": 8,
    "column": 23,
    "end_line": 8,
    "end_column": 32,
    "severity": "WARNING",
    "rule": "SystemVerilogUnconnectedInputs",
    "message": "Input not connected: 'rst_n'",

Show the full answer to “Where is the counter declared?”Hide the full answer to “Where is the counter declared?”

sv_find_symbol counter*

{
  "symbols": [
    {
      "name": "counter",
      "kind": "module",
      "file": "rtl/counter.sv",
      "line": 1,
      "column": 8
    },
    {
      "name": "counter_pkg",
      "kind": "package",
      "file": "rtl/counter_pkg.sv",
      "line": 1,
      "column": 9
    }
  ],
  "more": false,
  "timed_out": false
}

Your coding agent asks the IDE too

Your coding agent (Claude Code, Codex, Cursor, Junie) gets the same project knowledge through its MCP tools: references, module interfaces, the elaborated hierarchy, a check of code before it is written, and a dry-run rename.

Instead of guessing from the text with grep, the agent asks the IDE: where is this declared, what ports does this module have, who instantiates it, what does this macro expand to, is this file correct.

See what an agent can ask Coding agents (MCP)

Design Hierarchy

top top
u_counter counter
MAX int = 20

clkcountdone

slang 12.0.0

sv_hierarchy
sv_find_references
sv_check
sv_run

For you, in the editor

rtl/top.sv

8counter #(.MAX(20)) u_counter(.clk, .rst_n, .count(count), .done(done));

rtl/counter.sv

1module counter #(parameter int MAX = 10) (

2input logic clk,

3input logic rst_n,

4output logic [7:0] count,

5output logic done

Go to Declaration and Find Usages

Click a name and press ⌘B (Ctrl+B): the editor opens its declaration, in whichever file it is. Find Usages (⌥F7 / Alt+F7) lists where it is used, end labels included. Names are resolved the way a SystemVerilog tool resolves them, inner scopes first.

Go to Declaration Find Usages In the IDE: video

uvm/my_pkg.sv

28`uvm_component_utils(my_driver)

29virtual my_if vif;

…

48class my_agent extends uvm_agent;

49my_driver drv;

…

58class my_env extends uvm_env;

59my_agent agt;

…

64agt.drv.vif = null;

UVM that resolves

UVM testbenches reach their classes through handles, factory calls and config_db string keys. Go to Declaration, Find Usages and Rename follow these patterns, from vif.req to the signal. Strings such as the config_db key "vif" are left alone.

UVM testbenches In the IDE: Find Usages of my_if

rtl/counter.sv

11always_ff @(posedge clk or negedge rst_n) begin : seq

12if (!rst_n) begin

13count <= 0;

14state <= IDEL;

'IDEL' is not declared; did you mean 'IDLE'?

Change to 'IDLE'

15end

16else if (state == COUNT) begin

17count <= count + 1;

Undeclared names, with the fix

SystemVerilog Studio underlines an undeclared name such as IDEL as you type. When a declared name is spelt almost the same, it suggests that name and replaces it for you (⌥⏎ / Alt+Enter). A typo that Verilog would quietly turn into a new 1-bit wire, an implicit net, is reported as a warning, because the file would still compile.

Undeclared names In the IDE: screenshot

rtl/counter.sv

7import counter_pkg::*;

9state_t state;

count

Conflicts Detected

'count' is already declared in this scope

Usage of 'state' in 'state <= IDLE' would refer to another declaration of 'count'

CancelRefactor Anyway

Rename with conflict checks

Rename changes only the names that refer to this declaration, in all files. Before it changes a file, it checks that the new name keeps the meaning of your code. If the new name would re-bind a usage, you see a warning and can cancel.

Rename Rename conflicts In the IDE: screenshot

rtl/counter.sv

1module counter #(parameter int MAX = 10) (

slang: design element does not have a time scale defined but others in the design do [MissingTimeScale]

2input logic clk,

3input logic rst_n,

4output logic [7:0] count,

5output logic done

6);

Compiler checks with slang

Some mistakes only show up when the whole design is compiled together. Once slang is installed (one click in Settings), SystemVerilog Studio compiles your design with it each time you save a file. Its messages start with slang: and appear in the editor next to the IDE's own checks.

Compiler checks

Design Hierarchy

top top

clk input logic

rst_n input logic

u_counter counter

MAX int = 20

g_lane

[0]

[1]

i integer = 1

The elaborated design hierarchy

The Design Hierarchy tool window shows the design elaborated: built from the top module down as a compiler builds it, with each parameter's actual value and generate loops unrolled. It comes from slang-server, the language server of the slang compiler, which starts in the background when you open the window. Without slang-server, the window shows the static hierarchy instead, with parameters as written.

Design hierarchy Install slang

Code | Expand AUTOs

fifo u_fifo (/*AUTOINST*/

// Outputs

.rd_data (rd_data[WIDTH-1:0]),

.full (full),

.empty (empty),

// Inputs

.clk (clk),

…

.rd_en (rd_en));

verilog-mode AUTOs

Write /*AUTOINST*/ where an instance's port connections go. Code | Expand AUTOs connects each port to a signal of the same name, with vector ranges shown. This is Emacs verilog-mode's AUTO feature, so files written for it open and edit like any other.

Expand AUTOs

Run

…/verilator --lint-only -f …/sim.f

…

%Warning-WIDTHEXPAND: rtl/counter.sv:18:17: Operator EQ expects 32 bits …

%Error: Exiting due to 3 warning(s)

Process finished with exit code 1

rtl/counter.sv

18if (count == MAX - 1) state <= DONE;

Run Verilator and Icarus

SystemVerilog Studio runs Verilator and Icarus Verilog as run configurations, started with the Run button. The output appears in the Run tool window, and each file:line in it is a link to the source. You install the simulators; the IDE runs them.

Run configurations Verilator Icarus Verilog In the IDE: screenshot

sim_tb.vcd

clkcountdone

0d0e0f1011121314

225 ns

See the waves in Surfer

A Waveform Viewer run configuration opens a .vcd or .fst file in Surfer or GTKWave. You go from a run to its waves with one click instead of typing the viewer's command. The viewer is a separate application on your PATH.

Waveform viewer In the IDE: screenshot

See all features

For your team

Licences through JetBrains Marketplace. The IDE manages the licence with your other JetBrains licences, registered with a JetBrains account. Licensing
Compatibility. IntelliJ-based IDEs 2025.2.2 and newer. Tested on IntelliJ IDEA, including Community; checked for CLion and PyCharm with JetBrains Plugin Verifier. Compatibility
Support. Write to Hello@SystemVerilogStudio.com.

Talk to us about your team

Tell us who you are and how many engineers would use it. You get a reply by email.

Prefer to talk? Book a 30-minute call. Buying for a company? Pay by invoice or purchase order, or agree volume pricing: ask on the call or write to Hello@SystemVerilogStudio.com.

More for teams: licensing, compatibility and technical questions

Install in three steps

SystemVerilog Studio is a plugin: you install it from JetBrains Marketplace, from inside an IDE of version 2025.2.2 or newer.

Open the Plugins page of the settings (⌘, on macOS, Ctrl+Alt+S on Windows and Linux).
On the Marketplace tab, search for SystemVerilog Studio and click Install.
Click Restart IDE when it is offered, then register your code or licence.

Installation Register a code or licence

Plans and prices

Free evaluation
A 2-month code by email.
Get a free 2-month code
For individuals
$10 per month or $100 per year (2 months free) for a personal licence.
For companies
$50 per seat per month or $500 per seat per year (2 months free) for a commercial licence. Invoice or purchase order: see the page for teams.

When your code expires, buy a licence on JetBrains Marketplace to keep using SystemVerilog Studio. See the plans in full

Free for students, teachers and open-source projects through JetBrains Marketplace. How to apply

Latest blog posts

Why RTL Engineers Are Moving to SystemVerilog Studio for Hardware Development
RTL and verification engineers are discovering that IntelliJ IDEA, long known as a software development platform, now supports a purpose-built plugin for SystemVerilog design and testbench work. SystemVerilog Studio brings real-time, IEEE standard-compliant error checking and project-wide navigation to an IDE already trusted for large, complex codebases.

All blog posts

Start with a free 2-month code

Enter your email address and SystemVerilog Studio sends a 2-month code by email. No account or payment details needed.

Get a free 2-month code Talk to us about your team

The SystemVerilog IDE your coding agent can use too.

Your coding agent asks the IDE too

For you, in the editor

Go to Declaration and Find Usages

UVM that resolves

Undeclared names, with the fix

Rename with conflict checks

Compiler checks with slang

The elaborated design hierarchy

verilog-mode AUTOs

Run Verilator and Icarus

See the waves in Surfer

For your team

Talk to us about your team

Install in three steps

Plans and prices

Free evaluation

For individuals

For companies

Latest blog posts

Why RTL Engineers Are Moving to SystemVerilog Studio for Hardware Development

Start with a free 2-month code